It is often desirable to be able to program control words into a semiconductor device after its manufacture. These control words may control the functionality of the device and/or may be coefficients for adjusting operating parameters of the device in order to meet some desired specification.
A well known way of providing a reliable non-volatile memory which can be written to only once is a cross coupled pair of transistors as shown in FIG. 1. It can be seen that the arrangement includes a first fuse 2 arranged in series with a first transistor 4, and a second fuse 6 arranged in series with a second transistor 8. The transistors 4 and 8 are field effect transistors and the gate of the transistor 4 is connected to a node between the fuse 6 and the transistor 8 and the gate of the transistor 8 is connected to a node between the fuse 2 and the transistor 4. Source terminals of the transistors are connected to the ground supply rail and the fuses 2 and 6 are connected to the positive supply rail VDD. In order to program this arrangement the fuses 2 and 6 have to be selectively blown with one of the fuses being left intact. Thus, if the output of this memory cell is represented by the node 10, then in order to write a “1” into the memory the fuse 6 must be left intact whereas the fuse 2 must be blown, thereby making it high impedance. This means that the gate of the transistor 4 will be held high by virtue of the low impedance connection through the fuse 6 to the positive supply rail VDD whereas the gate of the transistor 8 will be held low due to the low impedance path to ground through the transistor 4. This makes a stable configuration which will always return to its correct state, even after power up, whilst also consuming essentially no current since ideally no current flows through the fuse 2 and transistor 4 since the fuse 2 is blown, and no current flows through the fuse 6 and transistor 8 because the transistor 8 is held hard off by virtue of its gate being connected to ground through the transistor 4. Therefore this memory circuit is very reliable. In practice a blown fuse often exhibits a high impedance but is not “non-conducting”. Hence a small current may be drawn through the “blown” fuse and then through the series transistor which is switched on.
Unfortunately this memory circuit can occupy a relatively large amount of space on a silicon die. The fuses 2 and 6 are typically fabricated as a silicon or poly-silicon bridge between two metal contacts. As the currents required to blow the fuse are relatively large (compared to the currents that normally flow within the integrated circuit) then the power connections to the fuse are correspondingly larger. A further problem is that the transistors in series with the fuses need to be able to pass sufficient current to blow the fuse in the first place. This generally results in two transistors being fabricated for each fuse. Thus in FIG. 1 transistor 4 is an active transistor to the memory cell whereas transistor 4a is provided solely to pass the fuse blowing current. Similar transistors 8 and 8a are provided on the other limbs of the memory cell. As a result these fuse blowing transistors 4a, 8a are very large compared to the size of a transistors 4 and 8 which are fabricated merely for a logic gate and are provided solely for conducting the fuse blowing current during device programming. Therefore, in summary, although the arrangement shown in FIG. 1 makes a reliable memory cell, it is relatively bulky on the silicon die and this is disadvantageous as there is often competition for space on the silicon die between different parts of the circuit fabricated thereon.
This problem has been recognised in the prior art and more compact memory cells, such as that shown in FIG. 2 have been described. The arrangement shown in FIG. 2 only comprises one fusible element 12 in series combination with a transistor 14. An output of the memory cell is represented by the node 16. In general, the transistor 14 is held off until it is desired to read the memory. When a memory read is performed, a test voltage is applied to the gate of the transistor 14 so as to turn the transistor 14 on. If the fuse is intact, then the fuse will pass sufficient current to hold the output node 16 at a “1” even though current is passing through the transistor 14. However if the fuse 12 has been blown then the transistor 14 causes the node 16 to be pulled to ground. Once again during a memory write operation it is required to pass sufficient current through the fuse 12 in order to blow it. This is typically performed by fabricating a larger fuse blowing transistor 18. In any event it can be seen that this memory arrangement occupies approximately half the area of the memory cell shown in FIG. 1. However it passes relatively large currents during a memory read process if the fuse is intact whereas the memory shown in FIG. 1 does not pass large currents although as noted hereinbefore some current flow does occur. Thus space on the die has been traded for power consumption. Additionally the switching on and off of the transistor 14 can give rise to current fluctuations which can perturb the performance of other circuits.
Power consumption is, of course, often critically important. Therefore the prior art also teaches that the arrangement shown in FIG. 2 can be modified, as shown in FIG. 3, to include a RAM cell 20 which can be used to capture and hold the content of the memory cell in response to a short test pulse applied to the gate of the transistor 14. This means that current only needs to be passed by the memory cell during a relatively brief read cycle and the result can then be latched into the RAM cell 20 which is typically fabricated as a static RAM such that once it has latched the result it doesn't pass any further current (theoretically). The fabrication of the RAM cell 20 typically only requires a few relatively small transistors and hence the arrangement shown in FIG. 3 still occupies much less circuit area than the arrangement shown in FIG. 1.
Even with the modification shown in FIG. 3, the memory is still imperfect since noise on the power rails during the memory cell read cycle may result in it passing the wrong value during a read cycle. It is dangerous for any semiconductor manufacturer to assume that the users of the product can conspire to place it in a low noise environment with a stable supply. Therefore, it is common practise for the arrangement shown in FIG. 3 to be periodically polled in order to refresh the contents of the memory cell 20. This improves the integrity of the circuit but does increase its power requirements.
There is also a risk that a memory read may occur before the memory is polled to refresh its contents.